Design and Development of Efficient Energy Systems. Группа авторов
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(H1). The sum obtained from this F1, F2, and H1 propagated to the full adder (F3). The carry which obtained from the F1, F2, and H1 given to another full adder (F4). The sum obtained from the F4 and the carry obtained from F3 provided to (H2) half adder. The sum output from full adder (F4) is the sum of the compressor Y1, the carry which obtained from the half adder (H2) and the carry obtained from full adder (F4) given to the (H2) half adder. The sum output from this half adder (H2) is compressor output Y2. Half adder (H3) output is the final output as Y3 and Y4.
2.3.1.5 10:4 Compressor
In Figure 2.7, a 10:4 compressor is made of five full adders, five half adders, and one OR gate. The working principle of this compressor is three inputs given to the full adder (F1), another three inputs given to another full adder (F2), and another three inputs given to the full adder (F3). The sum of these three full adders (F1), (F2) and (F3) is given to full adder (F5) and carry given to the full adder (F4). The last input and the sum of the full adder (F5) is given to (H3) half adder. Carry signal of (FG5) full adder and the output sum of the (F4) full adder acts as input to half adder (H1).
Figure 2.6 Compressor 8 to 4.
Figure 2.7 Compressor 10 to 4.
The sum obtained from the half adder (H3) is the Y1 output of the compressor. The carry output of the (H3) half adder and sum of (H1) half adder (H1) acts as input to (H4) half adder. The sum obtained from half adder (H4) taken as output Y2. The carry of the full adder (F4) and half adder (H1) given to half adder (H2). The carry output of (H4) half adder and the sum output of (H2) half adder acts as input to half adder (H5). The sum obtained for half adder (H5) is taken as output Y3. The carry of half adder (H5) and half adder (H2) is given to the OR gate. The result obtained in this OR gate is taken as output Y4.
2.3.1.6 12:5 Compressor
In Figure 2.8, a 12:5 compressor is made of five full adders, two half adders, and two 4:3 compressors. The working principle of this compressor is three inputs given to the full adder (FF1), another three contributions given to the full adder (FF2), another three contributions given to the full adder (FF3) and the last three inputs given to the full adder (FF4). The sum obtained from these full adders (FF1), (FF2), (FF3), and (FF4) is given to 4:3 compressor (CV1), and carry is given to another 4:3 compressor (CV2). The sum obtained from 4:3 compressor (CV1) is the Y1 output of the compressors. The carry1 of the 4:3 compressor (CV1) and the sum of the 4:3 compressor (CV2) acts as input to the (H1) half adder. Output sum of half adder (H1) is taken as output Y2. The carry2 of 4:3 compressor (CV1), carry of (H1) half adder and carry1 of the 4:3 compressor (CV2) is given to the full adder (FF5). The sum which is obtained from this full adder (FF5) is taken as output Y3. The carry of this full adder (FF5) and carry2 of the 4:3 compressor is given to half adder (H2). The sum obtained for half adder (H2) is taken as output Y4 and carry is taken as output Y5. In this compressor, we will provide 12 inputs, and 5 outputs will be obtained.
Figure 2.8 Compressor 12 to 5.
Figure 2.9 Compressor 15 to 5.
2.3.1.7 15:5 Compressor
In Figure 2.9, 15:5 compressor architecture requires six full adder (FP1-FP6), two half adders (HP1-Hp2), and two 5:3 compressors (CP1-CP2). Working principle of 15:5 compressor is (IN1-IN3) inputs given to the full adder (FP1), (IN4-IN6) inputs given to the full adder (FP2), (IN7-IN9) inputs given to the full adder (FP3), inputs (IN10-IN12) are inputted to the FP4 and input (IN13-IN15) are inputted to the FP5. Output signal sum obtained from all these full adders (FP1), (FP2), (FP3), (FP4), and (FP5) is given to the 5:3 compressor (CP2) and carry is given to the 5:3 compressor (CP1). The sum obtained from the 5:3 compressor (CP2) is the output Y1 of the compressor. The carry1 of 5:3 compressor (CP2) and the sum of 5:3 compressor (C1) given to half adder (HP1). The sum obtained from half adder (HP1) taken as output Y2. The carry of this half adder (HP1), carry2 of 5:3 compressor (CP2) and carry1 of 5:3 compressor (CP1) given to full adder (FP6). The sum obtained from full adder (FP6) taken as output Y3. The carry of this full adder (FP6) and carry2 of 5:3 compressor (CP1) given to half adder (HP2). The sum which is obtained from half adder (HP2) is taken as output Y4 and carry is taken as output Y5.
2.3.1.8 20:5 Compressor
In Figure 2.10, 15;5 compressor made of seven full adders, three half adders, and two 7:3 compressors. The working principle of this compressor is understood as input (X1-X3) inputs applied to the full adder (FP11). (X4-X6) inputs are provided to full adder (FP2), (X7-X9) inputs are given to full adder (FP3), (X10-X12) inputs are given to full adder (FP4), (X13-X15) inputs are given to full adder (FP5), (X16-X18) inputs are given to full adder (FP6) and the last two inputs (X19-X20) are given to half adder (HP1). The sum obtained from this (FP1), (FP2), (FP3), (FP4), (FP5), (FP6), and (HP1) is given to 7:3 compressor (CP1) and carry is given to another 7:3 compressor (CP2). The sum obtained from 7:3 compressor (CP1) is the output Y1of the compressor.
Figure 2.10 Compressor 20 to 5.
The output carry1 of 7:3 compressor (CP1) and the sum obtained from 7:3 compressor (CP2) is given to half adder (HP2). The sum which is obtained from half adder (HP2) is taken as output Y2. The carry of half adder (HP2), carry2 of 7:3 compressor (CP1), and carry1 of 7:3 compressor (CP2) given to full adder (FP7). The sum obtained from full adder (FP7) taken as output Y3. The carry of this full adder (FP7) and carry2 of 7:3 compressor (CP2) given to half adder (HP2). The sum obtained from half adder (HP3) is taken as output Y4 and carry is taken as output Y5. Different compressor blocks are integrated to develop the architecture using the Boolean equation.
Figure 2.11 Behavioral simulation of 8x8 VM.
Figure 2.11 presents the simulated waveform of which obtained while we implemented the 8x8 Vedic Multiplier. We have given input for a specific time, and it goes to the end till which we have mentioned stop in the test bench. Here a is 8-bit input and b is 8-bit input, and we are getting 16 bit as output, and it is represented in p. The multiplier is implemented with Verilog HDL using the Xilinx