1 Chapter 3Table 3.1 Algorithm setting for wheelchair direction.

      2 Chapter 7Table 7.1 Strategy for investigating for IoT devices which help in proper chain ...Table 7.2 IoT’s chain of custody and challenges faced by investigators.

      3 Chapter 9Table 9.1 Pin details of the 8-bit square root.Table 9.2 Pin details of 8-bit multiplier.Table 9.3 Synthesis report of 8-bit multiplier.Table 9.4 Pin details of 8-bit up counter.Table 9.5 Synthesis report of 8-bit down counter.Table 9.6 Eight-bit down counter IP core synthesis report for Spartan-6 FPGA har...Table 9.7 Synthesis report of an 8-bit square root.Table 9.8 Synthesis report of 8-bit square root IP core.Table 9.9 Comparative table of conventional approach and IP core approach.Table 9.10 Spartan-3E FPGA hardware device utilization summary of different leng...Table 9.11 Spartan-6 FPGA hardware device utilization summary of different lengt...Table 9.12 Area and delay comparison with different FPGAs.Table 9.13 Area and delay comparison with different FPGAs.Table 9.14 Comparison with existing work.Table 9.15 Power calculation.

      4 Chapter 10Table 10.1 Compares the various architectures on the basis of the taxonomies, me...

      5 Chapter 11Table 11.1 Node description.Table 11.2 General comparison of AODV and DSDV

      6 Chapter 13Table 13.1 The physical state, liveness detection, and resolution of current fin...

      1 Chapter 1Figure 1.1 Fundamental steps of image processing in face recognition.Figure 1.2 Layers of the model.Figure 1.3 Structure of face recognition system.Figure 1.4 Block diagram of face recognition system.Figure 1.5 Components of the system.Figure 1.6 Welcome to the Raspberry Pi desktop.Figure 1.7 Setup.Figure 1.8 Options on display.Figure 1.9 Image of registration.Figure 1.10 LCD displaying door lock system.Figure 1.11 Unknown face recognized.

      2 Chapter 2Figure 2.1 WSNs connection to the internet.Figure 2.2 IoT-cloud-based remote health monitoring.Figure 2.3 Health monitoring using IoT-based Raspberry Pi.Figure 2.4 Healthcare monitoring model using RFID.Figure 2.5 Arduino-based health monitoring system.Figure 2.6 Healthcare system via IOT.Figure 2.7 Systemic model of health monitoring using ECG signal.

      3 Chapter 3Figure 3.1. Block diagram of gesture-based hand gloves using Arduino UNO.Figure 3.2. Circuit diagram of gesture-based hand gloves using Arduino UNO.

      4 Chapter 4Figure 4.1 Chimeras designed through gene targeting (source: https://en.wikipedi...Figure 4.2 Plasmid method in a bacterial cell.Figure 4.3 Cloning DNA of interest using the vector method.Figure 4.4 Biolistic gene gun.Figure 4.5 BtCotton.Figure 4.6 Flavr-Savr.Figure 4.7 Global adoption rates for biotech crops (million hectares).Figure 4.8 Global adoption rates for biotech crops (million hectares).Figure 4.9 Recent trends in gene therapy research and clinical trials. (a) Diffe...Figure 4.10 CRISPR technology mechanism.

      5 Chapter 5Figure 5.1 Describes the subdomains of AI forensics [S].Figure 5.2 AI in GPS navigation.Figure 5.3 Challenges on implication of AI.

      6 Chapter 6Figure 6.1 Model explaining the interrelation of mobility forensics with mobile ...Figure 6.2 Diagrammatic representation of internal structure of smart devices.Figure 6.3 (a) The email says “referring email id that Rs. 5,000,000 loan amount...Figure 6.4 Common model explaining the process of forensic investigation for IoT...Figure 6.5 Factors related to the IoT mobility forensics.Figure 6.6 Model explaining drawback of internet of things in forensics.

      7 Chapter 7Figure 7.1 IoT architecture to understand data flow.Figure 7.2 The loopholes of the IoT ecosystem.Figure 7.3 Mixture of three digital scientific schemes which helps in understand...Figure 7.4 IoT Forensics requires a multi-faceted approach where demonstration c...

      8 Chapter 8Figure 8.1 IoT sensors over business objectives.Figure 8.2 Encryption and decryption process.Figure 8.3 Symmetric encryption.Figure 8.4 Asymmetric encryption.

      9 Chapter 9Figure 9.1 Xilinx counter IP core.Figure 9.2 Binary counter IP core.Figure 9.3 RTL schematic of 8-bit down counter IP core.Figure 9.4 Binary counter IP core.Figure 9.5 RTL schematic of 16-bit up/down counter IP core.Figure 9.6 IP core generation wizard.Figure 9.7 Xilinx square root IP core.Figure 9.8 Square root IP core.Figure 9.9 Square root IP core.Figure 9.10 RTL view of 8-bit square root.Figure 9.11 RTL view of 8-bit square root.Figure 9.12 RTL view of 16-bit square root using IP core.Figure 9.13 RTL view of 8-bit multiplier.Figure 9.14 Simulation view of 8-bit multiplier.Figure 9.15 Xilinx multiplier IP core.Figure 9.16 Multiplier IP core.Figure 9.17 RTL schematic of 8-bit multiplier IP core.Figure 9.18 Eight-bit multiplier simulation using IP core.Figure 9.19 RTL view of 8-bit down counter.Figure 9.20 RTL schematic of 8-bit down counter IP core.Figure 9.21 Eight-bit down the counter simulation.Figure 9.22 Eight- bit down counter simulation using IP core.Figure 9.23 Sixteen- bit down counter simulation using IP core.Figure 9.24 Sixteen-bit up a counter simulation using IP core.Figure 9.25 Sixteen-bit down counter simulation using IP core.Figure 9.26 Eight-bit square root simulation.Figure 9.27 Eight-bit square root simulation using IP core.Figure 9.28 Square root simulation for a non-perfect square number using IP core...Figure