Design and Development of Efficient Energy Systems. Группа авторов
Читать онлайн книгу.
3 bits. The addition of higher input performed using compressors with compressor architectural addition of more than three inputs implemented with reduced architecture and improved speed [11].
Figure 2.1 Multiplication of two 8-bit number with Urdhwa-Tiryakbhyam Sutra [28].
2.3 The Architecture of 8x8 Vedic Multiplier (VM)
The hardware architecture of 8x8 multiplier explained below is dependent on Urdhva-Tiryagbhyam. The advantages of VM algorithms found as generation of partial product and performed synchronously. It enhanced the parallel processing and preferred for the implementation of the binary multiplier. An 8x8 Vedic multiplication block diagram, presented in Figure 2.2 implemented as a binary equation is given below. Each stage generates partial product, term as carrying. This carry input added with the next step of a partial product. Here requires adder can accept multiple data together. A full adder is a basic unit that can provide three data together. A compressor derived from the adder used to implement numerous inputs [12–16]. A 4:3 compressor accepts four inputs and maps the result into three output signals. 8x8 VM hardware architecture requires adding 20 input bits together, which is implemented with 20:5 compressor.
(2.1)
(2.2)
(2.3)
(2.4)
(2.5)
(2.6)
(2.7)
Figure 2.2 Block diagram of 8*8 multiplier.
(2.8)
(2.9)
(2.10)
(2.11)
(2.12)
(2.13)
(2.14)
(2.15)
(2.16)
2.3.1 Compressor Architecture
The combinational block requires to implement the more multiple are logical AND, OR, XOR. To perform addition half adder and full adder are preferred. The compressor can perform the addition of the higher number of inputs; the compressor focused. The compressor is made up of an adder block. The compressor maps a piece of higher information to lower the number of outputs with summation operation. A full adder is basic 3:2 compressor units of 3:2. It accepts three numbers of input and map as a sum and carries at the output terminal.
Figure 2.3 Compressor 3:2.
2.3.1.1 3:2 Compressor
In Figure 2.3, the compressor is made of two XOR gates and a MUX Gate and by which we obtain the outputs as the sum and carry. The working principle of 3:2 compressor is similar to full adder, but delay, power, and time of 3:2 compressor is much lower than that of a full adder.
2.3.1.2 4:3 Compressor
In Figure 2.4 the compressor is made of three half adders and one full adder by which we obtain the outputs as the sum and two carries. The working principle of 4:3 compressor is to understand as two of the inputs applied to the half adder (H1), and the other two inputs are applied half adder (H2). The sum of two half adders given to (H3) half adder and the sum which obtained from (H3) is the sum of the compressor, and the carry which derived from all the half adders inputted to full adder. Sum and carry output of this full adder is named as SUM2 and carry is SUM3.
2.3.1.3 5:3 Compressor
In Figure 2.5 5:3 a compressor is shown which is composed of two full adder (F1 & F2) and one-half adder. The working principle of this 5:3 compressor understood as, out of five three are the input to the full adder (F1). Sum output obtained from this full adder and the other two inputs applied to another full adder (F2).
The sum which derived from this full adder is the sum of the compressor, and the carry which obtained from those two full adders given to half adder, the sum of this half adder is taken as SUM2 and carry as SUM3.
Figure 2.4 Compressor 4:3.
Figure 2.5 Compressor 5:3.
2.3.1.4 8:4 Compressor
In Figure 2.6, an 8:4 compressor is composed of four full adders (F1-F4) and three half adders (H1-H3). The working principle of this compressor is analyzed as three inputs applied to the full adder (F1), and another three contributions given to another full adder (F2) and the last two inputs given to the half adder