Design and Development of Efficient Energy Systems. Группа авторов

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Design and Development of Efficient Energy Systems - Группа авторов


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result obtained from vertex-4 FPGA. An 8-bit VM requires 418 slices, 729 LUT and 67 IOB shown in Table 2.2. A similar effect is verified with cadence NCSIM and the implementation result confirmed with RTL compiler at gpdk 180nm technology. The simulation result shows that

Device utilization summary
Logic utilizations Used Available Utilization
Slices 418 1672 4%
4 input LUTs 729 17344 4%
Bounded IOBs 67 250 26%

      The case I Input A=8’d136 and B=8’d119 result in multiplier values p=16’h16184.

      Case II Input A=8’d141 and B=8’d124 result in multiplier values p=16’h17484.

      Case III Input A=8’d145 and B=8’d129 result in multiplier values p=16’h18834.

      The performance parameter of 8-bit VM is judged by power consumption, delay, and area report obtained by the cadence RTL compiler. Completed implementation of an 8-bit Vedic multiplier is through the combinatorial block. The usage of the compressor reduces the requirement of resources. As the number of the logic gate but increases the interconnecting wires. Similarly, area requirements to interface multiple compressors significantly enhance the area and delay. In this section area, power and delay are presented due to logical resources and wires.

      2.4.1 Instance Power

Pie chart depicts instance power usage of 16 by 16 VM.

      2.4.2 Net Power

Pie chart depicts net power usage of 16 by16 VM.

      2.4.3 8-Bit Multiplier

Instance Cells Cell area Net area Total area Wire load
Vedic Multiplier 139 1517 0 1517 <none> (D)
Instance Cells Leakage power(nW) Dynamic power(nW) Total
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